1. Field of Invention
This invention relates to electronic circuitry and more particularly to connecting a field effect transistor to a flip-chip carrier.
2. Description of the Prior Art
The amount of power that can be provided by a field effect transistor (FET) is limited by the amount of power that the FET can safely dissipate. When the FET is mounted in a heat sink, there is a large increase in the amount of power that can be safely dissipated and, correspondingly, a large increase in the amount of power that can be provided. In one particular arrangement, the FET is mounted in a flip-chip carrier type of heat sink. The flip-chip carrier is referred to and shown in the article, "Thermal resistance of GaAs Power FETs" by H. C. Huang, F. N. Sechi and L. S. Napoli in the Proceedings of the Sixth Biennial Cornell Electrical Engineering Conference (1977).
To understand the mounting of the FET in the carrier, it should be understood that the FET is comprised of a plurality of unit transistors with a substrate common to all of the unit transistors.
An exemplary unit transistor includes three elements, one of which is a thin metal deposition, known as a unit gate, that forms a Schottky barrier junction with the substrate. The other two elements, known as a unit drain and a unit source, respectively, are each a thin metal deposition in ohmic contact with the substrate.
The unit sources usually have metal posts plated thereon that are axially perpendicular to the substrate. The distal surfaces of the posts have displacements from the substrate greater than the displacements of the distal surfaces of the unit gates and the unit drains. The FET is mounted with the distal surfaces of the posts in contact with a flat surface of the carrier. Because the distal surfaces of the posts have the greater displacement from the substrate, the flat surface does not make contact with either the unit gates or the unit drains.
The carrier is typically connected to a ground plane, such that all of the unit sources form a grounded source electrode of the FET. Since a wire is not used to connect the source electrode to ground, there is no introduction of an undesirable inductance in series with the source electrode, as found in other heat sink arrangements.
It is often desirable to introduce a resistor, in parallel with a capacitor, between the source electrode and ground. A DC bias current flows through the resistor to establish a voltage between the source electrode and ground thereby obviating a need for a bias power supply. Additionally, when the bias current increases, for example, the source to ground voltage increases thereby tending to decrease the bias current. Accordingly, the resistor introduces a negative feedback that tends to stabilize the bias current thereby making the operation of the FET uniform over a wide temperature range.
The use of the resistor and the capacitor is known as self biasing. However, self biasing is inconsistent with the connection of the source electrode to ground through the carrier. Heretofore, concurrently obtaining the advantages of self biasing and the flip-chip carrier has been unknown in the prior art.